The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 1995

Filed:

May. 26, 1993
Applicant:
Inventor:

Cecil H Kaplinsky, Palo Alto, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 39 ; 326 41 ;
Abstract

A logic circuit having a programmable first logic circuit stage and a fixed or dedicated combinatorial second logic circuit stage, serving as a macrocell for the first logic circuit stage. At least one input to the logic circuit is connected directly to the second stage, bypassing the first stage. The first stage may be a programmable logic device with a programmable AND plane followed by an OR plane, and is functionally flexible. The second stage has at least two groups of CMOS logic gates arranged in sequence and connected in a fixed manner by hardwiring so as to implement a specified combinatorial logic function that is representable in sum-of-products form, and is fast compared to the first stage. The outputs from the first stage control logic operations of the second stage upon the directly connected input or inputs.


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