The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 1995
Filed:
Dec. 16, 1994
Bradley J Larsen, Woodland Park, CO (US);
Todd A Randazzo, Colorado Springs, CO (US);
Geoffrey S Gongwer, Campbell, CA (US);
Atmel Corporation, San Jose, CA (US);
Abstract
An EEPROM transistor fabricated with a single polysilicon layer. An MOS transistor is fabricated with a subsurface electrode region defined by a stripe in a first direction. A layer of thin oxide is arranged in a second stripe, perpendicular to the first stripe and a polysilicon layer, arranged in a third stripe is disposed over the second stripe of thin oxide. An adjoining parallel plate capacitor is formed by a subsurface region of the same conductivity type as the subsurface electrodes in the first stripe. An insulative second plate of thin oxide is joined to the second stripe and a third plate of the capacitor is formed by a polysilicon plate over the oxide plate. Vertical metallization stripes in the first direction may contact with some components, while parallel metal stripes in a second layer in a perpendicular direction may contact with the remaining members. The stripe geometry allows lateral and vertical four-way symmetry for implementation of a large number of memory storage cells on a chip or wafer.