The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 1995
Filed:
Aug. 24, 1993
William D Mensch, Jr, Mesa, AZ (US);
Other;
Abstract
The topography of an 84 lead CMOS microcomputer chip includes first, second, third, and fourth consecutive edges, with chip control logic being located along the upper left edge. The chip includes six multiplexed peripheral I/O port buffer circuits, a data bus buffer port, chip control logic, tone buffers, and system speed control circuitry located around the edge of the periphery of the chip. One of the six ports functions as a parallel interface bus. The microcomputer includes a sixteen bit W65C816S CMOS microprocessor, 576 bytes of SRAM, 8192 bytes of SROM, a plurality of edge interrupt inputs and level-sensitive interrupt inputs, four UARTs, eight timers, priority interrupt control circuitry, and two tone generators. The topography is arranged to provide convenient connection of terminals of the microcomputer when it is used as a 'core' of a larger computer system chip including an external memory system, a serial communication system, and an interrupt and I/O system. A system speed control system allows automatic programmed selection of the system clock speed to achieve efficient accessing of various different speed on-chip memories, off-chip memories, and peripheral devices so as to minimize power dissipations.