The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 1995

Filed:

Aug. 16, 1993
Applicant:
Inventors:

Mitsuo Oshiba, Hachioji, JP;

Takefumi Sakurada, Akishima, JP;

Naoaki Tani, Hachioji, JP;

Takumi Sugaya, Hachioji, JP;

Takao Rokutan, Higashimurayama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B / ;
U.S. Cl.
CPC ...
369124 ; 369120 ; 369100 ;
Abstract

An optical information recording/reproducing device is constituted of a focus control circuit connected to a controller, a tracking control circuit, a data processing circuit, and a card feed control circuit. The data processing circuit includes a plurality of I/V converters for converting signals received by a plurality of signal reproducing light receiving elements arranged to an optical detector into current/voltage, and a plurality of binary circuits each for converting the output from the I/V converters into a binary signal in a reference level. The data processing circuit includes a selector for selecting at least two outputs of a plurality of binary circuits. The data processing circuit includes a plurality of bit-clock producing circuits and a plurality of demodulation circuits. The bit-clock producing circuits produce bit clocks based on binary signals originated from selectors and a plurality of binary circuits which are not connected to the selectors. The demodulation circuits executes sampling the two binary signals in accordance with bit clocks and executes data demodulation using the sampled results. The data processing circuit includes a plurality of memories storing demodulated results from the plurality of demodulation circuits.


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