Address transition detecting circuit of a semiconductor memory device

Abstract

An ATD circuit of a semiconductor memory device includes a variable delay line for delaying an address signal, a logic comparator for comparing the logic of the address signal with that of the address signal delayed by the variable delay line to generate an ATD pulse signal having a constant width at the rising and falling edges of the address signal, and a power supply voltage detector for detecting a voltage level of the power supply voltage to adjust the length of the variable delay line according to the voltage level, so that the pulse width of the ATD pulse signal for controlling precharge and voltage equalization of a bit line and operation of a sense amplifier is constantly maintained independently of the variation of a power supply voltage to thus improve access speed of the semiconductor memory device.