The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 1995
Filed:
Aug. 11, 1994
Lavi A Lev, San Jose, CA (US);
Sun Microsystems, Inc., Mountain View, CA (US);
Abstract
A fast static logic gate contains a pullup logic network and a pulldown logic network configured to implement a logic function. The pullup logic network is coupled to receive gate inputs, and generates a first voltage level at a first node to represent a first state in accordance with the gate inputs and logic function. The first voltage level is less than the source voltage for the fast static logic gate circuit. A leaker circuit generates a second voltage level at the first node in response to a second state of the logic function. A driver circuit is coupled to a second node for generating an output. The pulldown logic network receives the gate inputs, and generates a second voltage level for the output to represent the second state in accordance to the gate inputs and logic function. The switch circuit couples the first node to the second node when the logic function generates the second state, and couples the source voltage to the second node when the logic function generates the first state. In this way, the driver circuit receives a full source voltage representing the first state.