The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 1995
Filed:
Nov. 24, 1993
Raul-Adrian Cernea, Cupertino, CA (US);
SunDisk Corporation, Santa Clara, CA (US);
Abstract
A charge pump circuit comprises a plurality of voltage doubler circuits connected together such that a first voltage output generated by a first portion of a kth one of the voltage doubler circuits is substantially equal to Vdd*2.sup.k and Vdd*2.sup.k-1) on odd and even phases, respectively, of a first clock signal, and a second voltage output generated by a second portion of the kth one of the voltage doubler circuits is substantially equal to Vdd*2.sup.k-1) and Vdd*2.sup.k on the odd and even phases, respectively, of the first clock signal. Each of the voltage doubler circuits is constructed such that when its first portion is providing a voltage of Vdd*2.sup.k and a current to a next stage, its second portion is recharging a capacitor in that portion to Vdd*2.sup.k-1), and when its second portion is providing a voltage of Vdd*2.sup.2 and a current to the next stage, its first portion is recharging a capacitor in that portion to Vdd*2.sup.k-1). An output circuit is connected to a last one of the voltage doubler circuits to provide other circuitry with a substantially constant output voltage Vpp and output current Ipp, by providing such voltage and current from a first voltage output of the last voltage doubler circuit on odd phases of the first clock signal, and from a second voltage output of the last voltage doubler circuit on even phases of the first clock signal.