Electrostatic discharge protection transistor element fabrication process

Abstract

An electrostatic discharge protection (ESDP) transistor element is coupled at an input or output of an MOS integrated circuit (IC) device for protecting internal transistor elements of the MOS IC device from electrostatic discharge (ESD) dielectric breakdown voltages. A relatively thick passivating layer of low temperature deposited passivating material is deposited over the active area between the channel and gate of the ESDP transistor element. A metal layer gate is formed over the passivating layer. The channel insulating layer thickness provides a turn on voltage V.sub.TON less than the dielectric breakdown voltage BVGOX of internal transistor elements. The bond pads of the MOS IC device are used for the metal layer gates and the metal layer gate bond pads are formed over the active area of the ESDP transistor elements. The ESDP transistor elements are fabricated using the same mask sequence and associated mask steps as the internal transistor elements of the MOS IC device, modified to provide a thick oxide MOS (TOXMOS) metal gate ESDP transistor element.