The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 1995

Filed:

Aug. 30, 1993
Applicant:
Inventors:

Frederick J Aichelmann, Jr, Hopewell Junction, NY (US);

Cecil A Branson, Manassas, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 101 ;
Abstract

A fault tolerant memory system including a plurality of memory chips arranged to produce an array of addressable locations. Each addressable location has a plurality of data bits and a plurality of check bits for checking the integrity of all the data bits and check bits at a given addressable location. A pool of spare chips including at least two spare chips are available for assignment to replace any of the memory chips or a previously assigned spare chip in the event that a chip failure is identified. A memory maintenance facility for detecting and assigning spares, in response to the data bits and the check bits read from a given location in memory, is provided for detecting a failing memory chip or previously assigned spare chip and for assigning a previously unassigned spare chip to replace the failing memory chip or previously assigned spare chip.


Find Patent Forward Citations

Aichelmann, Jr, Frederick. (1995). Fault tolerant memory (U.S. Patent No. 5434868). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5434868

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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