Self-resetting cmos off-chip driver

Abstract

A self-resetting CMOS off-chip diver includes a first pair of complementary FETs connected in series to receive first and second complementary drive signals from an on-chip source. A latch is connected to an output of the first pair of complementary FETs for latching said drive signals. The first pair of complementary FETs in combination with the latch form a unique 'pulse catcher' circuit capable of catching and latching short duration pulses characteristic of the self-resetting (SR) mode, providing the transfer between the SR mode and the output static mode. A low power three state static driver circuit is comprised of first and second pass gates connected to pass an output of the latch and a second pair of complementary FETs respectively connected to receive outputs of the first and second pass gates to generate a static output for driving a transmission line. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the control means to provide a three state function output. The three state static circuit provides high speed data transfer with a high drive capability full swing signal output. An enable circuit implementing four enable functions, including a testability function, is connected to the first and second pass gates to inhibit an output to the second pair of complementary FETs in the test mode. Pull-up and pull-down devices are connected to respective inputs of the second pair of complementary FETs and controlled by the enable circuit to provide the three state function output, including a high impedance state.