Controllers request access within one bus cycle causing hardware-wait to

Abstract

A multi-CPU programmable controller which operates to access one of a plurality of I/O interface units through a common I/O bus for controlling one of a plurality of equipments each connected to each associated one of the I/O interface units. The programmable controller includes a pair of controllers, each of the pair including an individual CPU for generating an access signal for selectively accessing one of said I/O interface units through the common I/O bus for control thereof within one bus cycle. Each of the pair of controllers operates in accordance with a specific program independently from each other. The programmable controller further includes a base board for mounting controllers together with the common I/O bus as well as the I/O interface units: bus arbitrating device, provided on the base board, for generating a single sampling clock. The bus arbitrating device supervises the access signals from the pair of controller means such that the bus arbitrating device determines, when the two access signals from the controllers are respectively detected at the same timing within the one bus cycle, whether to provide priority to one of the pair of controllers over the other in accordance with a predetermined priority and to assume that one of the pair of controllers as a prior controller and the other one as a posterior controller.