Bicmos memory cell with current access

Abstract

A current mode access BiCMOS memory cell is disclosed. The memory cell includes a CMOS storage cell for storing first and second CMOS voltage potentials, VDD and VSS, corresponding to first and second logic levels. The storage cell includes two CMOS inverters coupled between VDD and VSS. The storage cell is coupled to a conversion circuit. The conversion circuit is coupled between third and fourth ECL working potentials. It functions to convert the first and second CMOS voltage potentials into the third and fourth working potentials. The third and fourth voltage potentials are coupled to the bases of two bipolar signal converters. The emitters of the bipolar signal converters are coupled to a selectable current source and the collectors of the bipolar signal converters are coupled to complementary bit lines. The selectable current source is responsive to a read word signal. A differential current signal representing the data stored in the memory cell is established in the complementary bit lines when the current source is selected and current is allowed to flow through one of the bipolar signal converters. The third and fourth ECL voltage potentials are chosen such that they ensure that the bipolar signal converters are not driven into saturation. In this way, read times are optimized. In addition, read times are reduced since peak-to-peak voltage of the current mode differential signal established across the complementary bit lines are reduced.