The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 1995

Filed:

Oct. 08, 1992
Applicant:
Inventor:

Amr Mohsen, Saratoga, CA (US);

Assignee:

Aptix Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
364490 ; 364489 ; 364488 ;
Abstract

A high I/O count integrated circuit is disposed on a semiconductor chip having opposing faces and comprises a plurality of functional circuit modules, each having inputs and at least one output having a first drive capability. A plurality of a first type of I/O nodes, each comprising a first conductive structure is disposed in a first I/O node array on the surface of a first one of the semiconductor chip faces. A plurality of a second type of I/O nodes, each comprising a first conductive structure is disposed on the first semiconductor chip face. An interconnect architecture comprising a plurality of conductors is superimposed on the functional circuit modules, the interconnect architecture comprises a plurality of interconnect conductors. Selected ones of the interconnect conductors are connectable to the inputs and at least one output of selected ones of the functional circuit modules by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to other selected ones of the interconnect conductors by user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the first I/O nodes by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the second I/O nodes by electrically programmable user-programmable interconnect elements.


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