The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 1995
Filed:
Oct. 20, 1994
Applicant:
Inventors:
Shuichi Moriyama, Niigata, JP;
Masayuki Shimura, Niigata, JP;
Assignee:
NEC Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ; H03K / ;
U.S. Cl.
CPC ...
327152 ; 327144 ; 327160 ; 395550 ;
Abstract
A frequency dividing circuit/delay circuit is provided to generate a plurality of system clock signals according to the combination of frequency division and the delay based on a fast-speed basic clock signal to determine according to the address signal from a central processing unit (CPU) what the operating cycle of the slave is to select a system clock of optimum frequency or duty ratio for that slave. As a result, it becomes possible to shorten the time required for executing one cycle and, hence, to improve the performance of the whole personal computer system.