The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 1995
Filed:
Mar. 31, 1994
Phuc Pham, Chandler, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A translator circuit (21) converts an ECL logic level to a TTL logic level. The translator circuit (21) operates at high speeds, rejects power supply noise, and does not use Schottky diodes for preventing transistors from saturating. The translator circuit comprises a differential input stage (22), a level shift stage (23), a differential stage (24), and an output stage (25). The differential input stage (22) is responsive to an ECL signal and provides a differential output signal. The level shift stage (23) level shifts the differential output signal of the differential input stage a predetermined DC voltage. The differential stage (24) is responsive to the level shift stage (23) and generates first and second output signals. The differential stage (24) rejects power supply noise coupled from the level shift stage (23). The output stage (25) is responsive to the first and second output signals of the differential stage (24) and converts the first and second signals to a single ended TTL signal corresponding to the logic level of the ECL signal.