The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 11, 1995

Filed:

Oct. 15, 1993
Applicant:
Inventors:

Jack T Wong, Fremont, CA (US);

Fabiano Fontana, Santa Clara, CA (US);

Henry Law, Cupertino, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 32 ; 326 33 ; 326 34 ; 326108 ;
Abstract

A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level. The several embodiments disclosed provide: 1) a high speed NOR gate that offers high speed performance on both the low-to-high and high-to-low transitions; 2) a high speed NOR gate for which voltage swings on the input circuits thereof are minimal; 3) a high speed NOR gate with pull-up current temperature and voltage compensation for improved performance on the low-to-high transition of the output; and 4) a high speed NOR gate using a feedback technique to regulate and limit the logic low voltage on the output such that this level has minimal variation independent of the number of the NOR inputs held in the logic high state.


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