The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 11, 1995
Filed:
Oct. 24, 1994
Kenneth K O, Boston, MA (US);
Analog Devices, Inc., Norwood, MA (US);
Abstract
A process for fabricating an IGFET integrated circuit having two gate dielectric layers with different parameters is provided. Typically, the process is used for fabrication of dual voltage CMOS integrated circuits. The integrated circuit may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness. A first gate dielectric layer and a first gate layer for the high voltage transistors are formed over active regions of a substrate. The device is patterned to expose low voltage transistor areas, and the first gate dielectric layer and the first gate layer are removed in the low voltage transistor areas. Then, a second gate dielectric layer and a second gate layer for the low voltage transistors are formed on the device. The device is patterned to expose the high voltage transistor areas, and the second gate dielectric layer and the second gate layer are removed in the high voltage transistor areas. The gate dielectric layers are protected against contamination during processing and do not come in contact with photoresist.