Mechanism for efficiently releasing memory lock, after allowing

Abstract

A logic circuit mechanism for inducing a processing unit to release a LOCK signal that the processing unit uses to secure continuous access to a memory system during read modify write operations requiring 'atomic' (continuous) access. The processing unit has an internal cache enabling it to set up consecutive memory access operations at a pace such that the LOCK signal could be held continuously active while a string of atomic memory accesses is carried out. The present circuit mechanism prevents premature release of the processing unit's LOCK signal, by asserting a Hold signal which requires the processing unit to release its LOCK signal but only after that unit has fully completed its current atomic access operation. The logic circuit reduces its impact on processing unit performance by detecting when the LOCK signal has been active continuously for N consecutive atomic operations coinciding with external contention, and calling for release of the CPUs LOCK signal only while the Nth such operation is being conducted.