The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 1995
Filed:
Sep. 21, 1994
Vadim B Minuhin, Oklahoma City, OK (US);
Vladimir Kovner, Oklahoma City, OK (US);
Steven V Holsinger, Oklahoma City, OK (US);
Shafaollah Dahandeh, Norman, OK (US);
Seagate Technology, Inc., Scotts Valley, CA (US);
Abstract
A maximum likelihood detector for a disc drive in which data files are stored along tracks as a sequence of magnetically written data elements that give rise to a signal in the disc drive read chapel. The detector includes even and odd Viterbi decoders that determine the most likely even and odd subsequences of data elements from even and odd samples of the signal and a postcoder that generates the most likely sequence of bits of encoded user data from the subsequences. Each Viterbi decoder includes an analog adder and an analog subtracter for generating the sums and differences of each sample and a reference signal, a sample and hold circuit codected to the adder and subtracter to receive the sums and differences, a difference circuit that generates the difference between the contents of the sample and hold circuit and each sample, a comparator assembly that generates a two bit merge indicator signal from the output of the difference circuit and the reference signal, AND gates that transmit bits of the indicator signal to switches in the sample and hold circuit for entering the sum or difference of the sample and reference signal into the sample and hold circuit, a shift register having interstate decoders that transmit logical 1's in response to a specific nonzero bit of the merge indicator signal and an indicator bit while otherwise transmitting a logic value determined by the logic value received from a preceding stage of the shift register and a pointer for generating indicator bits for each sample for which the merge indicator signal is logical 00.