The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 04, 1995

Filed:

Sep. 01, 1993
Applicant:
Inventor:

William A Chren, Jr, Jenison, MI (US);

Assignee:

Grand Valley State University, Allendale, MI (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
375308 ; 364718 ; 331187 ;
Abstract

A direct digital frequency synthesizer employs residue number system based processors to generate output waveforms of desired frequencies. The frequency synthesizer includes a phase accumulator comprising a plurality of individual adders, each adding a predefined quantity to a digit of a frequency setting word in which the individual digits are residue digits of differing moduli. The outputs of the independent adders form a combined residue output word which is used to address a memory storing signal samples. In one embodiment of the invention, the memory is a dual port ROM storing samples of one-quarter of a sine wave and the dual port ROM is simultaneously addressed to read a selected sample and an associated sample corresponding to the magnitude of a sample of the sine wave advanced by 90.degree. from the first sample. A sample select logic circuit selects one of the outputs of the dual port memory on the basis of selected bits of the combined residue word and data bits stored in the ROM with the samples to select and determine the sign of the sample of the sine wave. In another embodiment of the invention, the memory comprises a plurality of independent memories, corresponding to the number of independent adders, each storing residue information and a residue processing array processes the residue data obtained from the independent memories and provides a residue encoded signal to a residue-to-analog converter which generates the desired analog output.


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