System and method for performing high-sped cache memory writes

Abstract

A system and method for improving cache memory write cycle timing in a microprocessor system, having static random access memory (SRAM) cache memory, using two out-of-phase clock signals and delayed variants thereof. The present invention includes the steps of sending a write address to the cache memory at a positive transition of the first out-of-phase clock signal that marks the beginning of the write cycle; causing a write control signal to be asserted at a time marked by next occurring positive transition of the second out-of-phase clock signal; sending the data to be written to the SRAM at a time marked by a drive clock signal; and ending the write cycle at a time marked by a end-write clock. The drive clock signal is provided by delaying the first out-of-phase clock signal. The amount of delay introduced in providing the drive clock signal is selected to allow the SRAM sufficient time to tri-state its drivers after receiving the write-control signal. The end write signal is provided by delaying the second out-of-phase clock signal. The amount of delay introduced in providing the end-write clock is selected to allow the SRAM sufficient time to read data to be written off of the data bus. The delay is introduced into the clock signals using printed circuit trace delay lines. The length of the printed circuit trace delay lines is selected such that the drive clock and end-write clock transitions occur at the optimum time.