The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 20, 1995

Filed:

May. 19, 1993
Applicant:
Inventor:

Hirohisa Machida, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364760 ;
Abstract

The multiplier includes a register circuit for holding a multiplicand X, a multiplier register circuit for holding a multiplier Y, a second order Booth decoder circuit for decoding prescribed less significant bits of the multiplier Y according to the second Booth algorithm, and a third order Booth decode circuit for decoding more significant bits of the multiplier Y according to the third Booth algorithm. A tripled of the multiplicand X is produced in a 3X producing circuit in parallel with a multiplication operation utilizing the second Booth algorithm in an adder array. The output of adder array together with the output of 3X producing circuit is applied to an adder array for executing a multiplication operation according to the third order Booth algorithm. Production of an odd number multiple data of the multiplicand necessary for the third order Booth algorithm is executed in parallel with the multiplication operation according to the second order Booth algorithm, and therefore time required for producing the triple can apparently be eliminated. Thus, a multiplier capable of executing multiplication at a high speed in a hardware manner is provided.


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