The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 1995
Filed:
Feb. 05, 1993
Fujitsu Limited, Kanagawa, JP;
Fujitsu VLSI Limited, Aichi, JP;
Abstract
A product-sum operation unit including a multiplying unit, a pipeline register for loading a multiplication result, an adder unit for adding a summand and either an output of the pipeline register or an addend. A timing signal generating unit generates first and second timing signals (T1, T2) that are synchronized with first and second clocks (CK1, CK2). A first instruction latch loads an instruction synchronously with the first timing signal (T1) to output a first control signal. A second instruction latch loads an instruction loaded in the first instruction latch synchronously with the second timing signal (T2) to output the second control signal. A control signal selector outputs the second control signal in response to the first timing signal (T1), and also outputs the first control signal to the adder unit, in response to the second timing signal (T2).