Electrically programmable inter-chip interconnect architecture

Abstract

A user-programmable inter-chip interconnect architecture, which may be used for providing programmable interconnections among a plurality of integrated circuits, is disclosed. A plurality of main circuitry in the core region of an integrated circuit is connected through connection nodes to a programmable peripheral switch network in the frame region of the integrated circuit. The peripheral switch network may be programmed by the user to obtain the desired signal-propagating paths between said connection nodes and bonding pads of the peripheral switch network, or among bonding pads of the peripheral switch network. The peripheral switch network has intersecting wiring channels attached to the bonding pads and the connection nodes. Programmable junctions may be present at the intersections of the wiring channels. A substantial number of desired interconnections may be achieved that have only one such programmable junction in the signal-propagating path. When a plurality of integrated circuits including this architecture arc mounted on a substrate that provides fixed conductive leads between the bonding pads of the integrated circuits, user-programmable, highly flexible, high-performance two-point and multi-point connections among the main circuitry of the integrated circuits are obtained.