Optimal pcb routing methodology for high i/o density interconnect devices

Abstract

An optimal routing methodology for routing high I/O density packages which minimizes the number of PCB layers required. One feature of this routing methodology comprises treating respective I/O that are routed at the top layer of the package as surface mount technology (SMT) pads without dropping vias within the BGA grid, as is commonplace in the industry. This facilitates the use of fewer escapes and allows for more efficient use of the available space. Signal lines on the top layer of the package which must be routed to other layers of the PCB are connected to vias outside of the area of local high signal density on the printed circuit board. The placement of vias outside the area of local high density, i.e., in a depopulated area, reduces the number of layers necessary in the PCB to properly route the signals. This placement also facilitates the use of filtering capacitors to meet EMI requirements. In addition, all voltage pins are placed on the innermost or outermost grids and have clearanced vias. The device is also preferably placed at the beginning or at the end of the bus to maximize the routing efficiency.