The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 1995
Filed:
Jul. 06, 1992
Kenneth W Jones, Austin, TX (US);
Ray Chang, Austin, TX (US);
Motorola Inc., Schaumburg, IL (US);
Abstract
An ECL-to-CMOS buffer having a single-sided delay comprises an ECL logic gate, a level converter, a plurality of series connected inverters, and a NOR gate. The ECL logic gate receives an ECL level input signal, and provides complementary intermediate level logic signals. The level converter receives the intermediate level logic signals and provides a CMOS level output signal. The NOR gate receives the CMOS level output signal, via the series connected inverters, at an input terminal after a predetermined delay. One of the intermediate level logic signals is also received by the NOR gate at a second input terminal. The CMOS level output signal is delayed for a predetermined time in a low-to-high transition, with no unwanted delay in a high-to-low transition.