Performance enhanced intergrated circuit layout methodology

Abstract

A performance enhanced simulation modeling technique is provided for optimizing integrated circuit layout. The modeling technique utilizes a performance enhanced methodology. Namely, a physical design enhances performance design to ensure that the simulation model takes into account placement and interconnect when determining whether or not the resulting integrated circuit will operate properly at required speed with actual load being applied. An initial sizing of selected devices within a network is performed using estimated time duration and load factors. Subsequently, select devices are resized according to more optimal physical time duration and load. The entire simulation modeling is achieved using computer program simulation prior to the generation of a final layout placeable upon a silicon substrate. As such, simulation methodology provides a flow to correct unexpected performance errors resulting from physical design.