The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 1995

Filed:

Jan. 04, 1993
Applicant:
Inventors:

Gerold W Neudeck, West Lafayette, IN (US);

Stephen J Duey, Noblesville, IN (US);

Assignee:

Purdue Research Foundation, West Lafayette, IN (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 63 ; 437 74 ; 437 78 ; 437 89 ; 437 90 ; 437956 ; 257565 ;
Abstract

A quasi-dielectrically isolated (QDI) bipolar structure using epitaxial lateral overgrowth (ELO) uses a combination of dielectric isolation (DI) and junction isolation (JI), providing better isolation properties than JI, while providing better heat dissipation than DI. ELO silicon is grown out of a deep basin with oxide sidewalls for lateral dielectric isolation. The ELO silicon is grown at a low temperature and pressure in an RF heated pancake-type reactor. Fabricated transistors have gains, ideality factors, and leakage currents comparable to bulk devices. A main application for QDI is in power integrated circuits (PICs) where isolation of high power devices and low power logic is necessary.


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