Differential gain stage for use in a standard bipolar ecl process

Abstract

An improved differential gain stage for a bipolar monolithic integrated circuit. The integrated circuit is formed from a semiconductor substrate, and the differential gain stage includes first and second bipolar transistors. The base of the first transistor and the base of the second transistor form a differential input for the gain stage comprising non-inverting and inverting inputs respectively. The collectors of the transistors form a differential output. The differential gain stage includes a capacitor stage comprising: a peaking capacitor, and first, second, third and fourth capacitor structures. The peaking capacitor is coupled between the emitters of the first and second transistors. The first and second capacitor structures are located at a first spaced relationship from the substrate and the first capacitor is coupled to the emitter of the first transistor and the second capacitor is coupled to the emitter of the second transistor. The third and fourth capacitor structures are located at a second spaced relationship from the substrate. The third capacitor is connected to the first capacitor and the connection forms a first node. The fourth capacitor is connected to the second capacitor and the connection forms a second node. The differential gain stage also includes first and second buffers. The first buffer has an input connected to the non-inverting input of the gain stage and an output connected to the first node. The second buffer has an input connected to the inverting input of the gain stage and an output connected to the second node.