Apparatus and method for testing packaged integrated circuits

Abstract

The present invention discloses an apparatus for testing an integrated circuit (IC) chip having a plurality of testing ports, each of the testing ports being used for connection with an testing interface assembly for further connection with external testing equipment. The apparatus includes a testing platform having a top surface, the top surface includes a chip placement means for securely placing the IC chip therein. The testing platform further includes a plurality of guiding posts extending upwardly from the top surface. The testing apparatus further includes a frame-housing which has a plurality of inter-connected walls, each of the walls further has an inner surface including an inner beam attached thereon. The inner surface and the inner beam define an elongated vertical space corresponding to each of the guiding posts of the testing platform. Each of the walls near the inner beam further includes an access means which has a plurality of openings allowing access of the testing interface assembly for connecting with the testing ports on the IC chip. Each of the guiding posts further including a locking means whereby when the frame-housing sliding along the guiding posts fitting each of the elongated vertical spaces defined by the inner wall surfaces and the inner beams thus surrounding the corresponding guiding post, the locking means further securely locks the frame-housing onto the testing platform.