The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 1995

Filed:

Feb. 22, 1993
Applicant:
Inventors:

Satoshi Saito, Ikoma, JP;

Keizo Sakiyama, Kashihara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437228 ; 437233 ; 437241 ; 437187 ; 437982 ;
Abstract

A method for a wiring layer on a semiconductor substrate wherein a contact hole for a wiring layer is formed by laminating a lower insulating layer and an etching barrier layer on the semiconductor substrate providing electrodes via a gate insulating film, forming a hole in the etching barrier layer using a first mask pattern having a hole pattern in which a diameter of the hole thereof is larger than that of the contact hole to be formed, laminating an upper insulating layer and a second mask pattern having a hole pattern in which a diameter of the hole thereof is substantially the same as that of the contact hole, subjecting the lower and upper insulating layers and the gate insulating film to an isotropic etching and an anisotropic etching, utilizing the second mask pattern, thereby forming a contact hole having no exposure of the etching barrier layer at the side of wall of the contact hole.


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