The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 1995
Filed:
Apr. 12, 1993
Peter D Hunt, Pleasanton, CA (US);
Jon K Elliott, Pleasanton, CA (US);
Richard J Tobias, San Jose, CA (US);
Alan J Herring, San Jose, CA (US);
Craig R Morgan, San Jose, CA (US);
John A Hiller, Palo Alto, CA (US);
Loral/Rohm Mil-Spec Corp., San Jose, CA (US);
Abstract
A method is employed for pre-assignment and pre-scheduling of tasks that enables allocation across multiple physical processors arranged in a variety of architectures. The method comprises the steps of: constructing a DFG of tasks to be performed to provide a solution for a problem; determining cost values for each task and the overall problem, such cost values taking into account a target multiprocessor architecture and factors such as elapsed task execution times. The method pre-assigns the tasks to logical processors and assures that inter-dependent tasks are executable by logical processors that are within required communications delay criteria of each other. The assigning action attempts to arrive at a minimal cost value for all tasks comprising the problem. The pre-assigned tasks are then pre-scheduled based upon a performance criteria and are converted to machine code. The machine code is then deployed to physical processors in the target multi-processor architecture. The deploying action maps the logical processors' pre-assigned programs (comprising assigned tasks) onto physical processors, using data regarding the multi-processor architecture and the current utilization of the physical processors in the architecture, all while assuring that inter-dependent tasks are mapped so as to fulfill interprocessor communication delay criteria.