The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 1995
Filed:
Mar. 28, 1994
Jay T Cantrell, Dallas, TX (US);
Edward R Schurig, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method and apparatus for a time domain boundary bridge circuit for capturing an event on an asynchronous input is described, comprising an S-R latch coupled to an asynchronous input, a first D flip-flop coupled to a synchronous clock and the output of the S-R latch, and a second D type flip-flop coupled to a synchronous clock and the output of the first D flip-flop, and having an output coupled to a circuit output terminal, operable to provide a synchronous output which reflects an event occurrence on the asynchronous input. A second embodiment is disclosed for use in systems where the asynchronous input signal is accompanied by a clock or strobe signal comprising a first D type flip-flop clocked on the strobe signal coupled to the asynchronous input signal, a second D type flip-flop clocked on a synchronous clock and coupled to the output of the first D type flip-flop, a third D type flip-flop coupled to the output of the second D type flip-flop and driving a circuit output terminal, and self clearing logic which clears the first D type flip-flop when the event is synchronously transmitted on the circuit output. A third embodiment is disclosed wherein the second embodiment additionally comprises rapid self-clearing logic improving the throughput rate possible on the asynchronous input signal. Other embodiments are also disclosed.