Synergistic multiple bit error correction for memory of array chips

Abstract

A two-level multiple bit error correction scheme includes at the first level a memory chip with a memory error detection capability that produces a chip error signal (CES) when it detects errors in the bits leaving that chip and at the second level an off-chip ECC facility which interprets generated syndrome bits and chip error signals in order to determine which bits are bad. There are two types of codes distinguished by the absence or presence of parity bits. The use of parity bits allows for the detection of single bit errors in data read from the chip. Therefore, the CES is active only for detected multiple bit errors. Chips not using parity bits are less expensive, but the CES must be active for both single bit and multiple bit errors.