Semiconductor memory device

Abstract

A semiconductor memory device comprises a word lines (15), pairs of complementary data lines (17, 18), memory elements (MC11) respectively arranged at each intersection of the word lines and the pairs of complementary data lines, pairs of complementary signal lines (17s, 18s) each associated with a sense amplifiers (SA) and selectively connected to one of the pairs of complementary data lines via a pair of transfer gate transistors (7, 8), first precharge means (5, 6) for charging the pairs of complementary data lines and second precharge means (19, 20) for charging the pairs of complementary signal lines. The second precharge means charge the pairs of complementary signal lines to a first voltage (V.sub.D), the first precharge means charge the pairs of complementary signal lines to a second voltage (V.sub.D -V.sub.t) which is smaller than the first voltage by a threshold voltage (V.sub.t) of the transfer gate transistors and the transfer gate transistors have their gate electrodes supplied with the first voltage. The transfer gate transistors are N-channel type MOS transistors and the first and the second precharge means include N and P channel MOS type transistors respectively.