Bit line load circuit for semiconductor static ram

Abstract

In a semiconductor static RAM which includes at least one static RAM memory cell connected to a pair of complementary bit lines and each connected to a different word line. A bit line load circuit is connected between the pair of complementary bit lines and a voltage supply potential, and a column selection circuit is connected between the pair of complementary bit lines and a pair of complementary common data bus lines coupled to an input/output data control circuit. The bit line load circuit includes a pair of precharge P-channel insulated gate field effect transistors connected between the voltage supply potential and the pair of complementary bit lines. A bit line equalizing P-channel insulated gate field effect transistor is connected between the pair of complementary bit lines. A gate of each of these P-channel transistors is connected to receive the same internal precharge signal. A pair of bit line level compensating N-channel insulated gate field effect transistors are connected in parallel to the precharge P-channel transistors, respectively, and the gate of each of the pair of bit line level compensating N-channel transistors is connected to the voltage supply potential.