The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 1995
Filed:
May. 28, 1993
Applicant:
Inventors:
Neil S Hastie, Plymouth, GB;
David A Williams, Plymouth, GB;
Assignee:
Plessey Semiconductors Limited, Wiltshire, GB;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326113 ; 327408 ;
Abstract
A programmable logic cell has two inputs and six outputs, each output being a different logical function of the inputs. Each output is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs and the other transistor of each pair having its gate connected to the inverse of the same input.
Hastie, Neil. (1995). Logic cell using only two n type transistors for generating each logic (U.S. Patent No. 5418480). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5418480
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile