The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 1995

Filed:

Jun. 17, 1994
Applicant:
Inventor:

Masakazu Shoji, Warren, NJ (US);

Assignee:

AT&T Corp., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 52 ; 437 29 ; 437 40 ; 437 48 ; 148D / ;
Abstract

A method for fabricating read-only memory ('ROM') devices utilizing junction field-effect transistors ('JFETs') having a conductive channel orthogonally oriented with respect to the surface of the semiconductor material composing the JFET. A fixed-position ion beam is employed to create this narrow gate channel, which extends between the JFET's source and drain contact. Employing such JFETs as basic memory sites within a semiconductor ROM circuit allows for an architecture that conforms to a minimum lattice structure layout. In addition, the resulting ROM offers high speed access of data. Although JFETs have not been utilized as the transistor of choice within ROMs because of their seemingly inferior performance when compared to MOSFETs, the invention provides a novel architecture which significantly enhances the practicality of the JFET as a memory device.


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