Apparatus and method for testing circuit board interconnect integrity

Abstract

Apparatus for testing the integrity of a plurality of conductive circuit connection paths between output pins on a first integrated circuit and input pins on a second integrated circuit on a circuit board includes first boundary scan cells associated with each output pin on the first integrated circuit, each of the first boundary scan cells adapted to selectively place a data test bit loaded therein onto the one of the output pins with which it is associated, second boundary scan cells associated with each input pin on the second one of the integrated circuits, each of the second boundary scan cells adapted to selectively store the digital value present on the one of the input pins with which it is associated, a controller for loading a data test bit into each of the boundary scan cells associated with each output pin on the first one of the integrated circuits, for respectively placing each of the data test bits onto respective ones of the output pins of the first integrated circuit, for selectively storing into each of the second boundary scan cells in the second integrated circuit the digital values present on the ones of the input pins associated therewith, and for comparing the digital values with the data test bits. Apparatus for observing circuit nodes in an analog integrated circuit includes a multiplexer connected to a plurality of circuit nodes to be observed, a sample/hold circuit for holding voltages obtained from the selected nodes, and a controller responsive to external signals for controlling the operation of the multiplexer and the sample/hold circuit.