The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 1995
Filed:
Aug. 07, 1992
Makoto Hasegawa, Tokyo, JP;
Kazuaki Takahashi, Kawasaki, JP;
Masahiro Mimura, Tokyo, JP;
Kazunori Watanabe, Yokohama, JP;
Katsushi Yokozaki, Yokohama, JP;
Hiroyuki Harada, Kawasaki, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An FSK data receiving system is provided which is capable of constituting a direct-conversion receiver suitable for realizing an integrated circuit, is capable of decoding in a wide receiving band width, and is capable of realizing a small-sized and less-electric power consumption data receiving. An FSK-modulated local oscillator signal 3 is applied to a local oscillator 2, and there is provided a decode circuit 15 which obtains the decode signal 14 by judging whether the FSK-modulated frequency deviation of the carrier wave signal 1 is a positive deviation or a negative deviation on the basis of a comparison result of a voltage change in a frequency-voltage conversion circuit 16 for a base-band signal 8; i.e. the output signal of a frequency mixer 6. An offset amount of the local oscillator frequency is judged by a voltage judging circuit 17 to produce a control signal 18 Further, there is provided another decode circuit 22 which makes a judgement of frequency change of the base-band signal 8 and a judgement of in-phase/opposite-phase relationship from the decode signal 14 and the output of the voltage judging circuit 17 so as to obtain a decode signal 23. Moreover, there is provided a decode signal processing circuit 25 which obtains a decode signal 24 from the decode signals 14, 23 in response to the control signal 18.