Semiconductor memory device having operation control means with data

Abstract

In accordance with the levels of input signals, a recall signal or store signal is generated and held. Based on the signal currently held, only one of the read/write timing circuit, recall timing circuit and store timing circuit is enabled for operation with the operation of the other two timing circuit disabled: the recall timing circuit is enabled when the recall signal is held, the store timing circuit when the store signal is held, and the read/write timing circuit when neither the recall signal nor the store signal is held. Therefore, once one operation mode has been selected by setting the input signals to a prescribed combination of levels, the selected mode is held until another operation mode is selected. Since there is no need to input the nonvolatile enable signal NE signal during the recall operation, the external input timing can be simplified. Even if noise appears on the write enable signal WE, there is no possibility of accidentally activating the store timing circuit, thus preventing the data from being destroyed. Before a main amplifying circuit commences the amplification operation, the potential of a common data line is biased to an intermediate potential which is between the power source potential and the ground level.