The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 1995
Filed:
Oct. 08, 1993
Yasushi Kubota, Sakurai, JP;
Shigeo Onishi, Nara, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A ferroelectric memory device according to the present invention comprises a plurality of bit lines carrying data signals and voltage signals, every adjacent two of the bit lines being paired to form a plurality of bit line pairs; sense amplifiers connected to each of the bit line pairs; a plurality of memory cells for storing data, each memory cell having a first capacitor and a first switching element, the first capacitor being connected to one of the bit lines via the first switching element, wherein the first capacitor includes a capacitor insulating film, at least one portion of the capacitor insulating film being formed of a ferroelectric material; a plurality of dummy cells for storing a reference voltage, each dummy cell having a second capacitor and a second switching element, the second capacitor being connected to one of the bit lines via the second switching element, wherein the second capacitor includes the capacitor insulating film at least one portion of the capacitor insulating film being formed of a ferroelectric material; a first common electrode line for controlling a voltage to be applied to the first capacitor; a second common electrode line for controlling a voltage to be applied to the second capacitor; a first word line for controlling the first switching element; and a second word line for controlling the second switching element, wherein a plurality of the memory cells and at least one of the dummy cells are connected to each bit line.