The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 1995
Filed:
Oct. 18, 1993
Dennis F Elwell, San Clemente, CA (US);
William R Crumly, Anaheim, CA (US);
Harold C Bowers, Rancho Palos Verdes, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
An inexpensive arrangement for mounting multiple, closely spaced integrated circuit chips (18, 20, 22, 24) on a low temperature co-fired ceramic (LTCC) substrate (10) uses a mandrel-produced thin film decal (26) having patterns of interconnecting conductive traces (34, 46, 47) that connect to the fine pitch connecting pads (60) of the integrated circuit chips at one end and connect to the relatively coarse pitch connecting pads (50) of the low temperature co-fired ceramic substrate at the other end. The interconnect decal is formed independently of the LTCC substrate and is provided with chip connections at a pitch of about 0.004 inches. The interconnect pads of the decal are connected by conductive traces on the decal to the LTCC pads which have a pitch in the order of about 0.01 inches or greater. The decal, which is formed independently of the LTCC substrate, is connected to the substrate pads by one of several different electrically conductive adhesives, including silver loaded epoxy, Z-axis conductive epoxy and anisotropically and isotropically conductive epoxy or low melting temperature solder. The decal enables use of a 'fan-out' arrangement in which connections are routed under the chip.