The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 1995

Filed:

Mar. 08, 1994
Applicant:
Inventor:

Mitsuru Sakamoto, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 60 ; 437 47 ; 437 52 ; 437919 ;
Abstract

In a semiconductor device comprising charge storage capacitors, each of which comprises a patterned electrode having electrode side and top surfaces, a dielectric film (22) on the side and top surfaces, and a covering electrode (23) on the dielectric film, the patterned electrode is composed of a lower silicon layer (26) having layer side and top surfaces and an upper silicon layer (27) lying on the layer side and top surfaces and having the electrode side and top surfaces. The dielectric film may be in direct contact with the electrode side and top surfaces. In this event, the lower silicon layer is preferably doped to a lower concentration between 10.sup.15 and 10.sup.18 atoms per cubic centimeter and the upper silicon layer, to a higher concentration between 10.sup.18 and 10.sup.20 atoms per cubic centimeter. Alternatively, a barrier metal film may be interposed between the dielectric film and the electrode side and top surfaces. In this event, each of the lower and the upper silicon layers is preferably doped to the lower concentration. More preferably, an amorphous silicon film is preliminarily deposited on micro-rough side and top surfaces of an underlying silicon layer to provide the upper silicon layer having smooth electrode side and top surfaces.


Find Patent Forward Citations

Sakamoto, Mitsuru. (1995). Method of making a semiconductor device comprising lower and upper (U.S. Patent No. 5411912). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5411912

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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