The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 02, 1995
Filed:
Oct. 25, 1993
Norihiro Ikeda, Ogaki, JP;
Kaoru Taketa, Gifu, JP;
Sanyo Electric Co., Ltd., Osaka, JP;
Abstract
A process for producing a semiconductor device comprises the following steps 1 to 9. In step 1, a field oxide layer is formed on a first conductivity type semiconductor substrate to define an active region. In step 2, gate electrodes, second conductivity type source regions and drain regions are formed on the active region, word line are formed on the field oxide layer, and an insulating layer is formed over the substrate. In step 3, contact holes are formed through the insulating layer so as to partly expose the source regions. In step 4, a polysilicon layer is formed over the exposed source region and the entire surface of the insulating layer. In step 5, a photoresist pattern is formed on the polysilicon layer. In step 6, the polysilicon layer is etched under etching conditions where selectivity to the insulating layer is high using the photoresist pattern as an etching mask to simultaneously form a storage pattern and trenches in the semiconductor substrate at the source regions. In step 7, the semiconductor substrate is doped along the storage electrode pattern and the inner surface of the trenches with a second conductivity type impurity. In step 8, a dielectric layer is formed on the doped storage electrode pattern and the doped inner wall surfaces of the trenches. Finally in step 9, an opposite electrode is formed on the dielectric layer.