The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 1995
Filed:
Oct. 18, 1993
Robert B Manley, Ft. Collins, CO (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A CMOS circuit for converting voltage levels between shifted differential ECL voltage level input signals and a CMOS voltage level signal. The ECL levels are referenced to the VDD voltage of the CMOS circuit and can be connected to ECL circuits that are connected between the CMOS VDD voltage and ground. The circuit has a pFET connected between a supply voltage and the output signal, and an nFET connected between the output signal and circuit ground. An inverted signal of the differential shifted ECL voltage input signals is connected to a gate of the nFET. A level shifting circuit connects the input signals to a gate of the pFET to ensure that it correctly drives the output signal when the input signals change logic levels.