Input buffer having an accelerated signal transition

Abstract

A CMOS buffer includes an input inverter, and a pull-up circuit coupled to the input inverter. The pull-up circuit provides an additional, temporary, signal pull-up on the output terminal of the input inverter during a high to low signal transition on its input terminal. The pull-up circuit includes a means for creating a signal delay. In one embodiment, the means for creating a signal delay includes a second and third inverter in series, the second inverter receiving an output signal from the input inverter. The pull-up circuit further includes two transistors for transferring a high signal to an output line of the input inverter. One transistor is controlled by a signal transferred by the means for creating a delay. The other transistor is controlled by an input signal to the input inverter. This pull-up circuit configuration ensures that the signal transition from low to high is substantially equal to the signal transition from high to low on the output line of the input inverter. The input inverter is then coupled to a driving circuit inverter to provide a CMOS buffer configuration.