The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 1995

Filed:

Jun. 18, 1992
Applicant:
Inventors:

Mikio Kyomasu, Hamamatsu, JP;

Masanori Sahara, Hamamatsu, JP;

Kenichi Okajima, Hamamatsu, JP;

Hiroyasu Nakamura, Hamamatsu, JP;

Assignee:

Hamamatsu Photonics K.K., Hamamatsu, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257458 ; 257446 ; 257514 ; 257517 ;
Abstract

This invention relates to a monolithic IC having a PIN photodiode and an n-p-n bipolar transistor formed on a single semiconductor (silicon) substrate. In fabricating such IC, it is important to electrically isolate the photodiode and the bipolar transistor. In addition it is necessary to make the surface of the substrate flat. According to this invention, the inter-device isolation between the above-described two devices is attained by forming two epitaxial layers on the silicon substrate, forming trenches in the layers, and burying silicon dioxide in the trenches. In the monolithic IC according to this invention wiring capacity is small, and high-speed performance becomes possible. A p-type buried-layer is formed below the bipolar transistor to thereby prevent punch through between the bipolar transistor and other devices. Also this invention provides the process for fabricating a planar type bipolar transistor suitable to fabricate the monolithic IC and also provides a PIN photodiode of a new structure.


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