Circuit for continuous processing of video signals in a synchronous

Abstract

A data processing apparatus includes a dual port data input register, first and second sequential ring counters, first and second register files, first and second data transfer circuits, a dual port data output register and N single bit processing elements. The dual port data input register has an M bit wide input port and an N bit wide output port. The first sequential ring counter cyclically selects one column of the data input register for input. The first data transfer circuit has a plurality of input segments, which are subsets of consecutive columns of the data input register. The first data transfer circuit transfers data from a selected row of the data input register to a selected row of the first register file for all columns of each input segment in a repetitive sequence of consecutive input segments in synchronism with said first sequential ring counter. The dual port data output register, the second register file, the second sequential ring counter and the second data transfer circuit are similarly organized to output data. Each of the N single bit processing elements is connected to a predetermined column of the first and second register files and capable of data processing operations under program control including data transfer to and from selected rows of said predetermined column of said first and second register files.