First order fll/pll system with low phase error

Abstract

A circuit includes both a frequency locked loop (FLL) and a phase locked loop (PLL) to control the frequency and phase of a controlled oscillator with respect to a data signal. The FLL includes a frequency setting register that provides a digital control word to a digital-to-analog converter for causing the frequency of the controlled oscillator to equal the frequency of the data signal. The PLL has a phase detector for causing the phase of the controlled oscillator to approximate the phase of the data signal. The inventive circuit also includes a lock detector for determining whether the phase error between the controlled oscillator and the data signal is constant. When phase lock is achieved, a counter is enabled to count a periodic reference signal and to produce an overflow signal when a given count is exceeded. The overflow signal is selectively coupled to the frequency setting register in order to reduce the phase difference between the controlled oscillator and the data signal. In this manner, low phase error may be obtained in a first-order PLL system, thereby avoiding jitter peaking associated with second-order PLL systems.